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Rprog output is limited to set voltage or current on DCP405

by | Feb 16, 2025 | Tasklist | 0 comments

fietser28

Make the rprog (voltage or current) honor the Vset/Iset limits.

In normal operation I always set things low to avoid magic smoke. With prog currently the voltage limit is completely off now. Looking into the schematics it doen’t look hard to implement.

Attached is my proposed hardware change. It implements:

  • limits the output voltage or current to the current set current (given by the DAC). The limit is set in software and enforced in hardware (for speed).

Except for the #93 part: It’s a design only! I did not test this in hardware!

Rprog changes2

Explanation of the schematic:

  • Allow external current programming? #87). I used a free pin (pin 6 of IC13) to turn Rprog for current on/of. This is analog to the voltage setting circuit.
  • The comparators LM293/LM393 compare the Rprog input voltage agains the output (Vset/Iset) voltages from the DAC. If the Rprog voltage is lower the analog switch will switch (thru AND gate) to the DAC output (where the limit should be set).

Impact on BOM:

  • TL072, LM293, 2N7002 and SN74LVC1G3157 are already use so more of the same components. Parts with annotated numbers are already present in the current DCP405.
  • New component is 74LVC1G08 (AND gate). I used a discrete logic gate to make sure the switching is fast (see the issue below).
  • I did not check the C and R component but they are very common values.

Needed software changes:

  • Addition menu to select current instead of voltage Rprog.
  • Turning on/off Rprog for current should make pin 6 @ic13 (GPB5) high/low.
  • During Rprog the set voltage or current should be send to DAC to set the upper limit (before turning Rprog on)

Possible issues.
There is a small race condition in this design: If Rprog steps above Vset/Iset, the signal will probably propagate thru the analog switch before it switches to the Vset/Iset limit due to the delay of the comparator, AND gate and switch. This is probably a very short period but is should be tested in the implementation if it is visible or problematic on the output (with or without load). E.q. will a step of Rprog above Vset/Iset cause an overshoot on the output of the DCP405?

Reference: https://github.com/eez-open/modular-psu/issues/94

  • New feature request