Status register programming lets you determine the operating condition of the instrument at any time.
This subsystem controls the SCPI-defined status-reporting structures. SCPI defines, in addition to those in IEEE 488.2, QUEStionable, OPERation, Instrument SUMmary and INSTrument registers. These registers conform to the IEEE 488.2 specification and each may be comprised of a condition register, an event register, an enable register. The purpose and definition of the SCPI-defined registers is described in "Volume 1: Syntax and Style". SCPI also defines an IEEE 488.2 queue for status. The queue provides a human readable record of instrument events. The application programmer may individually enable events into the queue.
STATus:PRESet enables errors and disables all other events.
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SCPI command |
Description |
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STATus |
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:OPERation |
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Returns the value of the Operation Event register |
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Returns the value of the Operation Instrument Condition register |
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Enables specific bits in the Operation Event register |
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:INSTrument[<n>] |
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Returns the value of the Operation Instrument Event register |
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Returns the value of the Operation Instrument Condition register |
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Enables specific bits in the Operation Instrument Event register |
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:ISUMmary<n> |
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Returns the value of the Operation Instrument Isummary Event register |
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Returns the value of the Operation Instrument Isummary Condition register |
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Enables specific bits in the Operation Instrument Isummary Event register |
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Presets all enable registers to power-on state |
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:QUEStionable |
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Returns the value of the Questionable Event register |
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Returns the value of the Questionable Condition register |
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Enables specific bits in the Questionable Event register |
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:INSTrument[<n>] |
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Returns the value of the Questionable Instrument Event register |
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Returns the value of the Questionable Instrument Condition register |
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Enables specific bits in the Questionable Instrument Event register |
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:ISUMmary<n> |
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Returns the value of the Questionable Instrument Isummary Event register |
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Returns the value of the Questionable Instrument Isummary Condition register |
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Enables specific bits in the Questionable Instrument Isummary Event register |
5.14.1. STATus:OPERation[:EVENt]?
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Syntax |
STATus:OPERation[:EVENt]? |
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Description |
This query returns the value of the read-only Operation Status Event register The bits are latched and reading the register will clear it. The *CLS command can be also used to clear the register. |
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Return |
The value returned is the binary-weighted sum of all bits set in the register. For example, if bit 9 (decimal value = 512) and bit 13 (decimal value = 8192) are set, this command will return 8704. See table in the Section 3.3 for bits description. |
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Usage example |
If GROUp PARallel (bit 8) is set (next query returns 0 since the first query clears the event register): STAT:OPER? 256 STAT:OPER? 0 |
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Errors |
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Related Commands |
*CLS *STB? STATus:OPERation:ENABle |
5.14.2. STATus:OPERation:CONDition?
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Syntax |
STATus:OPERation:CONDition? |
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Description |
This query returns the value of the read-only Operation Status Condition register. |
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Return |
The value returned is the binary-weighted sum of all bits set in the register. For example, if bit 9 (decimal value = 512) and bit 13 (decimal value = 8192) are set, this command will return 8704. See table in the Section 3.3 for bits description. |
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Usage example |
If GROUp PARallel (bit 8) is set: STAT:OPER:COND? 256 |
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Errors |
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Related Commands |
STATus:OPERation:ENABle |
5.14.3. STATus:OPERation:ENABle
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Syntax |
STATus:OPERation:ENABle {<value>} STATus:OPERation:ENABle? |
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Description |
This command and its query set and read the value of the Operation Status Enable register. The Enable register is a mask for enabling specific bits from the Operation Event register to set the operation summary bit 7 (OPER) of the Status Byte register. This bit is the logical OR of all the Operational Event register bits that are enabled by the Operation Status Enable register. |
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Return |
Query the Operation Status Enable register. The PSU returns a binary-weighted decimal representing the bits set in the enable register. |
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Parameters |
Name |
Type |
Range |
Default |
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<value> |
NR1 |
A decimal value which corresponds to the binary-weighted sum of the bits in the register (see the table in Section 3.3) |
PREset=0 |
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Usage example |
Enable ISUM (bit 13): STAT:OPER:ENAB 8192 |
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Errors |
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Related Commands |
*CLS *STB? STATus:OPERation[:EVENt]? |
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5.14.4. STATus:OPERation:INSTrument[:EVENt]?
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Syntax |
STATus:OPERation:INSTrument[:EVENt]? |
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Description |
This query returns the value of the read-only Instrument Operation Status Event register. The bits are latched and reading the register will clear it. The *CLS command can be also used to clear the register. |
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Return |
The value returned is the binary-weighted sum of all bits set in the register. For example, if bit 1 (decimal value = 2) and bit 2 (decimal value = 4) are set, this command will return 6. See table in the Section 3.3.1 for bits description. |
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Usage example |
If bit 2 (INST2) is set: STAT:OPER:INST? 4 |
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Errors |
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Related Commands |
*CLS STATus:PREset |
5.14.5. STATus:OPERation:INSTrument:CONDition?
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Syntax |
STATus:OPERation:INSTrument:CONDition? |
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Description |
This query returns the value of the read-only Instrument Operation Status Condition register. |
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Return |
The value returned is the binary-weighted sum of all bits set in the register. For example, if bit 1 (decimal value = 2) and bit 2 (decimal value = 4) are set, this command will return 6. See table in the Section 3.3.1 for bits description. |
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Usage example |
If bit 2 (INST2) is set: STAT:OPER:INST:COND? 4 |
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Errors |
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Related Commands |
STATus:PREset |
5.14.6. STATus:OPERation:INSTrument:ENABle
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Syntax |
STATus:OPERation:INSTrument:ENABle {<value>} STATus:OPERation:INSTrument:ENABle? |
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Description |
Enable bits in the Instrument Operation Status Enable register. The selected bits are then reported to the Operation Status Event register. |
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Return |
Query the Instrument Operation Status Enable register. The PSU returns a binary-weighted decimal representing the bits set in the enable register. |
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Parameters |
Name |
Type |
Range |
Default |
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<value> |
NR1 |
A decimal value which corresponds to the binary-weighted sum of the bits in the register (see the table in Section 3.3.1) |
PREset=0 |
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Usage example |
Enable INST1 (bit 1) and INST2 (bit 2): STAT:OPER:INST:ENAB 6 |
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Errors |
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Related Commands |
*CLS STATus:PREset |
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5.14.7. STATus:OPERation:INSTrument:ISUMmary[<n>][:EVENt]?
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Syntax |
STATus:OPERation:INSTrument:ISUMmary[<n>][:EVENt]? |
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Description |
This query returns the value of the read-only Instrument Isummary Operation Status Event register for a specific channel of the PSU represented by numeric value [<n>]. When [<n>] is omitted, the system queries the Instrument Isummary Operation Status Event register of the current channel. The bits are latched and reading the register will clear it. The *CLS command can be also used to clear the register. |
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Return |
The value returned is the binary-weighted sum of all bits set in the register. See table in the Section 3.3.2 for bits description. |
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Usage example |
If bit 8 (CV1) and bit 10 (OE1) on the channel 1 are set (256+1024=1280): STAT:OPER:INST:ISUM1? 1280 |
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Errors |
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Related Commands |
*CLS OUTPut:MODE? |
5.14.8. STATus:OPERation:INSTrument:ISUMmary[<n>]:CONDition?
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Syntax |
STATus:OPERation:INSTrument:ISUMmary[<n>]:CONDition? |
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Description |
This query returns the value of the read-only Instrument Isummary Operation Status Condition register for a specific channel of the PSU represented by numeric value [<n>]. When [<n>] is omitted, the system queries the Instrument Isummary Operation Status Condition register of the current channel. |
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Return |
The value returned is the binary-weighted sum of all bits set in the register. See table in the Section 3.3.2 for bits description. |
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Usage example |
If bit 8 (CV1) and bit 10 (OE1) on the channel 1 are set (256+1024=1280): STAT:OPER:INST:ISUM1:COND? 1280 |
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Errors |
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Related Commands |
OUTPut:MODE? |
5.14.9. STATus:OPERation:INSTrument:ISUMmary<n>:ENABle
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Syntax |
STATus:OPERation:INSTrument:ISUMmary[<n>]:ENABle {<value>} STATus:OPERation:INSTrument:ISUMmary[<n>]:ENABle? |
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Description |
Enable bits in the Instrument Isummary Operation Status Enable register for a specific channel of the PSU represented by numeric value [<n>]. When [<n>] is omitted, the system queries the Instrument Isummary Operation Status Enable register of the current channel. The selected bits are then reported to the Status Byte.
This command and its query set and read the value of the Operation Status Enable register. The Enable register is a mask for enabling specific bits from the Operation Event register to set the operation summary bit (OPER) of the Status Byte register. This bit (bit 7) is the logical OR of all the Operational Event register bits that are enabled by the Operation Status Enable register |
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Return |
Query the Instrument Isummary Operation Status Enable register. The PSU returns a binary-weighted decimal representing the bits set in the enable register. |
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Parameters |
Name |
Type |
Range |
Default |
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<value> |
NR1 |
A decimal value which corresponds to the binary-weighted sum of the bits in the register (see the table in Section 3.3.2) |
PREset=0 |
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Usage example |
The query returns that VOLT1 (bit 0), CURR1 (bit 1) and TEMP1 (bit 4) are set (1+2+16=19): INST? CH2 INST CH1 STAT:OPER:INST:ISUM:ENABLE? 19 |
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Errors |
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Related Commands |
*CLS STATus:PREset |
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Syntax |
STATus:PREset |
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Description |
This command clears all bits in the Enable registers. |
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Return |
None |
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Usage example |
STAT:PRE |
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Errors |
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Related Commands |
*CLS |
5.14.11. STATus:QUEStionable[:EVENt]?
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Syntax |
STATus:QUEStionable[:EVENt]? |
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Description |
Query the Questionable Status event register. The bits are latched and reading the register will clear it. The *CLS command can be also used to clear the register. |
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Return |
The PSU returns a decimal value which corresponds to the binary-weighted sum of all bits in the register. See table in the Section 3.4 for bits description. |
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Usage example |
If the error is detected in RTC (Real-time clock) circuit, the bit 3 (TIME) is set and this command returns 8: STAT:QUES? 8 |
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Errors |
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Related Commands |
*CLS |
5.14.12. STATus:QUEStionable:CONDition?
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Syntax |
STATus:QUEStionable:CONDition? |
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Description |
Query the Questionable Status condition register. |
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Return |
The PSU returns a decimal value which corresponds to the binary-weighted sum of all bits in the register. See table in the Section 3.4 for bits description. |
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Usage example |
If the error is detected in RTC (Real-time clock) circuit, the bit 3 (TIME) is set and this command returns 8: STAT:QUES:COND? 8 |
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Errors |
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Related Commands |
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5.14.13. STATus:QUEStionable:ENABle
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Syntax |
STATus:QUEStionable:ENABle {<value>} STATus:QUEStionable:ENABle? |
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Description |
Enable bits in the Questionable Status Enable register. The selected bits are then reported to the Status Byte. When <enable value> is set to 0, executing this command will clear the Questionable Status Enable register. |
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Return |
Query the Questionable Status Enable register. The PSU returns a binary-weighted decimal representing the bits set in the enable register. |
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Parameters |
Name |
Type |
Range |
Default |
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<value> |
NR1 |
A decimal value which corresponds to the binary-weighted sum of the bits in the register (see table in Section 3.4) |
PREset=0 |
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Usage example |
The query returns that TIME (bit 3), TEMPerature (bit 4) and ISUM (bit 13) are enabled (8+16+8192=8216): STAT:QUES:ENAB? 8216 |
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Errors |
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Related Commands |
*CLS STATus:PREset |
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5.14.14. STATus:QUEStionable:INSTrument[:EVENt]?
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Syntax |
STATus:QUEStionable:INSTrument[:EVENt]? |
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Description |
Query the questionable instrument event register. The bits are latched and reading the register will clear it. The *CLS command can be also used to clear the register. |
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Return |
The PSU returns a decimal value which corresponds to the binary-weighted sum of all bits in the register and clears the register. See table in the Section 3.4.1 for bits description. |
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Usage example |
Result of the query when INST1 (bit 1) and INST2 (bit 2) are set (2+4=6): STAT:QUES:INST? 6 |
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Errors |
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Related Commands |
*CLS |
5.14.15. STATus:QUEStionable:INSTrument:CONDition?
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Syntax |
STATus:QUEStionable:INSTrument:CONDition? |
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Description |
Query the questionable instrument condition register. |
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Return |
The PSU returns a decimal value which corresponds to the binary-weighted sum of all bits in the register and clears the register. See table in the Section 3.4.1 for bits description. |
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Usage example |
Result of the query when INST1 (bit 1) and INST2 (bit 2) are set (2+4=6): STAT:QUES:INST:COND? 6 |
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Errors |
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Related Commands |
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5.14.16. STATus:QUEStionable:INSTrument:ENABle
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Syntax |
STATus:QUEStionable:INSTrument:ENABle {<value>} STATus:QUEStionable:INSTrument:ENABle? |
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Description |
Set the value of the questionable instrument enable register. This register is a mask for enabling specific bits from the questionable instrument event register to set the instrument summary bit 13 (ISUM) of the Questionable Status register. The ISUM bit of the Questionable Status register is the logical OR of all the questionable instrument event register bits that are enabled by the questionable instrument enable register. |
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Return |
Query the Questionable Instrument Enable register. The PSU returns a binary-weighted decimal representing the bits set in the enable register. |
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Parameters |
Name |
Type |
Range |
Default |
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<value> |
NR1 |
A decimal value which corresponds to the binary-weighted sum of the bits in the register (see table in Section 3.4.1) |
PREset=0 |
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Usage example |
Set INST1 (bit 1) and INST2 (bit 2): STAT:QUES:INST:ENAB 6 |
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Errors |
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Related Commands |
*CLS |
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5.14.17. STATus:QUEStionable:INSTrument:ISUMmary[<n>][:EVENt]?
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Syntax |
STATus:QUEStionable:INSTrument:ISUMmary[<n>][:EVENt]? |
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Description |
Return the value of the Questionable Instrument Isummary Event register for a specific channel of the PSU represented by numeric value [<n>]. When [<n>] is omitted, the system queries the questionable instrument Isummary enable register of the current channel. The event register is a read-only register which holds (latches) all events. Reading the Questionable Instrument Isummary Event register clears it. The *CLS command can be also used to clear the register.
When the PSU is operating as a voltage source, bit 1 (CURRent) is set. When the PSU is operating as a current source, bit 0 (VOLTage) is set. When the output is unregulated (UR), both bits are set (for example, while the output is changing to a new programmed value or when the PSU is sinking instead of sourcing because down-programmer is active with battery with higher voltage then set output is connected). |
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Return |
The PSU returns a binary-weighted decimal representing the bits set in the enable register. See table in the Section 3.4.2 for bits description. |
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Usage example |
Result of the query when over-current protection (OCP) condition is detected (bit 9): STAT:QUES:INST:ISUM1? 512 |
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Errors |
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Related Commands |
*CLS |
5.14.18. STATus:QUEStionable:INSTrument:ISUMmary[<n>]:CONDition?
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Syntax |
STATus:QUEStionable:INSTrument:ISUMmary[<n>]:CONDition? |
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Description |
Return the value of the Questionable Instrument Isummary Condition register for a specific channel of the PSU represented by numeric value [<n>]. When [<n>] is omitted, the system queries the questionable instrument Isummary enable register of the current channel.
When the PSU is operating as a voltage source, bit 1 (CURRent) is set. When the PSU is operating as a current source, bit 0 (VOLTage) is set. When the output is unregulated (UR), both bits are set (for example, while the output is changing to a new programmed value or when the PSU is sinking instead of sourcing because down-programmer is active with battery with higher voltage then set output is connected). |
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Return |
The PSU returns a binary-weighted decimal representing the bits set in the enable register. See table in the Section 3.4.2 for bits description. |
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Usage example |
Result of the query when over-current protection (OCP) condition is detected (bit 9): STAT:QUES:INST:ISUM1:COND? 512 |
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Errors |
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Related Commands |
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5.14.19. STATus:QUEStionable:INSTrument:ISUMmary[<n>]:ENABle
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Syntax |
STATus:QUEStionable:INSTrument:ISUMmary[<n>]:ENABle {<value>} STATus:QUEStionable:INSTrument:ISUMmary[<n>]:ENABle? |
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Description |
Set the value of the Questionable Instrument Isummary Enable register for a specific channel of the PSU represented by numeric value [<n>]. When [<n>] is omitted, the system queries the Questionable Instrument Isummary Enable register of the current channel. The *CLS command can be used to clear the register.
This register is a mask for enabling specific bits from the Questionable Instrument Isummary Event register to set the Instrument Summary bit (bits 1 and 2) of the Questionable Instrument register. These bits are the logical OR of all the Questionable Instrument Isummary Event register bits that are enabled by the Questionable Instrument Isummary Enable register. |
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Return |
Query the value of the Questionable Instrument Isummary Enable register. |
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Parameters |
Name |
Type |
Range |
Default |
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<value> |
NR1 |
A decimal value which corresponds to the binary-weighted sum of the bits in the register (see table in Section 3.4.2) |
PREset=0 |
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Usage example |
Enable bits for all events on channel 2 – VOLT2 (bit 0, value=1), CURR (bit 1, decimal value=2), TEMP2 (bit 4, value 16), OVP1 (bit 8, value=256), OCP2 (bit 9, value=512), OPP2 (bit 10, value=1024), therefore the enable value is 1+2+16+256+512+1024=1811: STAT:QUES:INST:ISUM2:ENAB 1811 |
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Errors |
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Related Commands |
*CLS STATus:PREset |
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